ALU (2: Design) - Making an 8 Bit pipelined CPU - Part 22
In this video I outline the goals and design of the arithmetic and logic unit. The ALU can be broken down into a number of modules which will be spread over the next few build videos.
There are 3 flags in the ALU, in this video I pull them all together and add LED indicators. The zero flag is built by constructing an 8 input NOR gate from 2x5 input NOR gates (The 74LS260) and then merging the outputs with one of the gates from a 74LS21 2x4 input AND chip. This really should have been done with a 2 input AND gate but that one is what I had to hand.
Flag states (for arithmetic carry and logical carry) are held in the usual 74LS574 D-Type latch chip. There is no use of the flags outside of the ALU yet but eventually they will be connected back to the pipeline for conditional jumps etc.
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https://www.youtube.com/watch?v=rjho_rRwn0g
I'm trying to finalise the pipeline, so in this video I implement the contention handling logic I proposed in video 65. This should improve the instructions per clock slightly but most importantly it will making programming the cpu a bit easier.
I actually ended up being able to fit it all onto the exiting fetch breadboard, the result is one of the most packed breadboards to date in the build.
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https://www.youtube.com/watch?v=8Guvt8gU6xI
The fetch unit at the head of the pipeline started of with very little functionality, my additions today expand that to deal with situations where the fetch unit does not fetch and dispatch an instruction.
In this video I use the 74LS541 driver to control instruction fetching and use a one gate from a 74LS32 quad OR to control the program counter increment.
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https://www.youtube.com/watch?v=SpdK6cvBoAU
I hadn't planned on a multiply video but I had direct requests when I mentioned I was working on a multiply for my function. This is really just a stepping stone to bigger programs for me but I break down the theory of how it works including some optimisation for my processor. I'll revisit this at some point, I think I can get a few more cycles out of it but the final 8x8 multiply came in faster than the same operation on the original 8086/8088 so I can't complain.
Errata: About 4 minutes in I show a sequence of numbers as multiples of a 173, the 1382 is a typo, it should be 1384. (The binary is correct).
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https://www.youtube.com/watch?v=1bc_D_vKDiI
I've been learning to use some pcb design software and in this video I convert the 16 bit counter address registers to a schematic. I've attempted to record this a few times and aborted so apologies if my commentary on the design work is a little lacklustre. The video started out at nearly 2 hours, I've edited that down to about 20 minutes with liberal use of fast forward so hopefully that condenses it enough to be interesting.
I've been using EasyEDA, it's free and online. My current impression is that it's not perfect (Although I don't have any experience of other packages) but it's functional and the professional software gets very expensive.
One more step before I have to get the soldering iron out.
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https://www.youtube.com/watch?v=Ok4g0sK-x28
In this video I attempt to describe all the main 8 bit busses in the cpu design with an obvious focus on the main bus. This video is intended to separate out some explanation so I can get on with the build without missing parts of the "why" out, as I have in some of the earlier videos.
I may do a similar architecture video on the 16 bit busses later, there isn't anything I haven't covered but it's spread out in multiple videos and it would be nice to have a sub series that covers all the concepts.
Note: the exact assignment of inc/dec of the counter registers to pipeline steps show in this video is out of date, but the principles remain the same.
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https://www.youtube.com/watch?v=CdoOnfKA_ps
I’ve been wanting to add some kind of persistent storage to the build. In this video I discuss various options for persistent storage before building the interface to interface a 3.3v SD card to the system.
Most of the work to interface to the SD card is in the coding, I have an abridged version of the coding in this video, and a longer edit with more detail on the extras channel video here: https://youtu.be/EOA3qdR_joQ
0:00 Introduction
0:35 Selection Criteria
1:46 Device Options
2:48 Selection Grid
3:42 SD Cards
4:21 Level Shifting to 3.3v
6:22 3.3v Power!
7:44 Logic Level Shifting
11:07 Wiring the SD Card
12:19 Code Introduction
13:55 A Choice
14:17 SD_Init()
19:30 SD_ReadBlock()
21:52 SD_WriteBlock()
23:53 Final Test
25:00 Outro
George Foot’s floppy drive videos: https://www.youtube.com/playlist?list=PLWKtKD_FaUF4cy-llnKLnh0ZgZ0Nyt1mW
The Digikey Level shifting article: https://www.digikey.co.uk/en/blog/logic-level-shifting-basics
The Tutorial I was loosely following: http://www.rjhcoding.com/avrc-sd-interface-1.php
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https://www.youtube.com/watch?v=ho1tq_G-u3w
In this video I explain some timing issues I've identified and how to resolve them using the 74LS574 flip-flop chip. With this addition the 16 bit registers can both load a value from the bus and be selected to assert their value to the bus.
With this addition the address register is almost complete, there are just a few small additions and tests I'd like to run before designing the pcb to finalise the design for this component.
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https://www.youtube.com/watch?v=Y-QFKxI-eAI
I have the PCB's for the general purpose registers back from the prototype manufacturer (JCLPCB in this case). In this video I solder the first of them up and give it a test.
Apologies if I didn't always keep the work well centred, it's can be quite awkward doing this with a camera in the way.
This felt a lot smoother than my first pcb, the only issue was a resister that hadn't taken to the pad properly which I discovered as I was working. The module at completion seems to work perfectly.
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https://www.youtube.com/watch?v=2L5hqtMoNKo