Address registers (5: Schematic) - Making an 8 Bit pipelined CPU - Part 12
I've been learning to use some pcb design software and in this video I convert the 16 bit counter address registers to a schematic. I've attempted to record this a few times and aborted so apologies if my commentary on the design work is a little lacklustre. The video started out at nearly 2 hours, I've edited that down to about 20 minutes with liberal use of fast forward so hopefully that condenses it enough to be interesting.
I've been using EasyEDA, it's free and online. My current impression is that it's not perfect (Although I don't have any experience of other packages) but it's functional and the professional software gets very expensive.
I wanted to put something up to mark the year. Here is a little preview of multiple-channel audio with a seasonal theme and a preview of one of my new pcb's. Let's hope that next year is less "interesting".
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https://www.youtube.com/watch?v=Xo1x-2Ct6h8
In this video I show the steps I used to generate the music data for the different tunes I've had the circuit play. Starting with a midi mile I convert it down to something simple enough for the circuit to play. In future videos I'll extend this code as new features are added and hopefully end up with something that sounds a bit better.
Links:
Midicsv tool - https://www.fourmilab.ch/webtools/midicsv/
Midi file docs - http://www.music.mcgill.ca/~ich/classes/mumt306/StandardMIDIfileformat.html
Midi file - https://www.mfiles.co.uk/scores/early-one-morning.htm
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https://www.youtube.com/watch?v=Ne49h0HTtA8
I've hit a big milestone in my CPU Build, the core of the processor is complete. There will be a few refinements as I convert more of it over to PCB's but the underlying functionality of the processor is done.
As a demonstration and test I've implemented the "Sieve of Eratosthenes" it's an efficient prime number finding algorithm. I have two modifications from the simple form of the algorithm, even numbers are skipped entirely and the Sieve is segmented into blocks of 256 values. This prevents large delays between the early smaller primes as it fills in a larger table.
Read more about the Sieve here: https://en.wikipedia.org/wiki/Sieve_of_Eratosthenes
Or Eratosthenes himself here: https://en.wikipedia.org/wiki/Eratosthenes
The "instructions per cycle" I give in the video is approximate, I'll build some hardware for measuring it more precisely in the future but it's inline with expectations. There is a larger table of processors for comparison here: https://en.wikipedia.org/wiki/Instructions_per_second
That bit where I say "the last few evenings" may have been a gross understatement.
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https://www.youtube.com/watch?v=YxScH_ZQAZA
This is a bit of eclectic mix of parcels, most importantly I have received some parts and the pcb's for the memory bridge in my CPU Build. I am in lockdown like most people so deliveries are a bit of a lifeline, a couple of parcels sneaked in here that I wouldn't have selected for mailbag but I left in anyway. Expect a soldering/install/test video for that new pcb soon.
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https://www.youtube.com/watch?v=cDKT7FRxae4
I'm trying to finalise the pipeline, so in this video I implement the contention handling logic I proposed in video 65. This should improve the instructions per clock slightly but most importantly it will making programming the cpu a bit easier.
I actually ended up being able to fit it all onto the exiting fetch breadboard, the result is one of the most packed breadboards to date in the build.
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https://www.youtube.com/watch?v=8Guvt8gU6xI
The accessibility controller was created to make gaming more accessible. I wanted to experiment with creating some large button peripherals for it. My goals here were to minimise parts and printing simplicity.
Learn more about the controller here: https://youtu.be/9fcK19CAjWM
On a completely unrelated note, I have a new cutting mat and I was stunned during the editing to see how different the colour looked between cameras.
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https://www.youtube.com/watch?v=5jBTYftDDf4
This videos Sponsor: https://www.digitspace.com/?b638947aa8594599
Direct Link To this kit: https://www.digitspace.com/products/diy-kit/smart-track-vehicle-diy-kit-d2-1-kit?b638947aa8594599
This is the 2nd of 3 kits sent to me by Digitspace, I retained full creative control so all it really means is that I have a couple of extra kits in the project box.
This was quite a fun build, the instructions were not in English so I had to work out a few bits along the way.
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https://www.youtube.com/watch?v=mmLMC7C4h04
This video took far longer than I'd have liked, hopefully it was worth it. I've spoken before about a hardware divide being more complicated than I wanted to do for this cpu so in this video I write a divide function. I do add a couple of instructions to make the process smoother, primarily I add "subae" which is a predicated subtract (it only subtracts if the flags are in the correct state).
I finish up with a demonstration of the Fibonacci sequence, only this time it's outputting the values in nice human readable decimal. I was overjoyed to get this all working, I probably surpassed all the previous time coding for this cpu just for this video.
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https://www.youtube.com/watch?v=pnVH-7Iv0gc
Final bit of functionality to be added to the UART is hooking up the transmit FIFO. After getting that working I make the appropriate changes to the UART library necessary to interface it back into the CPU.
I've added a new microphone stand and this is the first time I used it for recording a video. The Quality is much improved (better signal to noise) but it is much more sensitive to me moving my head while wiring. I'll be more careful in future.
0:00 Introduction
1:37 Rewire
4:47 Build Transmit
17:06 Design Flaw?
19:35 Interface to CPU
20:39 Code
23:32 Test & Troubleshooting
25:36 Working
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https://www.youtube.com/watch?v=LIylX3WTWPY